参考文献/References:
[1] Altera Corporation.FPGA Performance Benchmarking Methodology[M/OL].San Jose(USA):Altera Corporation,2007.[2012-12-15].http://www.altera.com.cn/literature/wp/wpfpgapbm.pdf.
[2] Anderson J H,Wang Q.Area-efficient FPGA logic elements:architecture and synthesis[C]// The 16th Asia and South Pacific Design Automation Conference (ASP-DAC).Yokohama(Japan):IEEE Press,2011:369-375.
[3] Liu Fuqi.Verilog HDL Design and Practice[M].Beijing:Beihang University Press, 2012.(in Chinese)
刘福奇.Verilog HDL设计与实战[M].北京:北京航空航天大学出版社,2012.
[4] Samir Palnitkar.Verilog HDL:A Guide to Digital Design and Synthesis[M].NewJersey(USA):Prentice Hall PTR,2003.
[5] Qi Xiaolei,Cai Xueliang,Sun Dewei.Methods and principia of FPGA design using Veriog HDL[J].Electronic Test,2008(3):67-71.(in Chinese)
祁晓磊,蔡学良,孙德玮.用Verilog HDL进行FPGA设计的原则与方法[J].电子测试,2008(3):67-71.
[6] Cong J J,Minkovich K.Optimality study of logic synthesis for LUT-based FPGAs[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2007,26(2):230-239.
[7] Chen Zhihui. FPGA Technology Mapping Algorithm Research[D]. Shanghai: Fudan University, 2011.(in Chinese)
陈志辉.FPGA工艺映射算法研究[D].上海:复旦大学,2011.
[8] Yang Jingqiu. LUT-based FPGA Technology Mapping Algorithm Research[D].Chengdu: University of Electronic Science and Technology, 2006.(in Chinese)
杨劲秋.基于LUT结构的FPGA的工艺映射算法的研究[D].成都:电子科技大学,2006.
[9] Ken Chapman.Multiplexer Selection[M/OL].San Jose(USA):Xilinx Inc.2008.[2012-12-15].http:// www.xilinx.com/support/documentation/white_papers/wp274.pdf.
[10] Metzgen P,Nancekievill D.Multiplexer restructuring for FPGA implementation cost reduction[C]// Proceedings in the 42nd Design Automation Conference.New York:Association for Computing Machinery,2005:421-426.
[11] Gao Haixia.Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations[C]// The 6th International Symposium on Quality of Electronic Design(ISQED 2005).San Jose(USA):IEEE Computer Society,2005:370-374.
[12] Betz V,Marquardt A,Rose J.Architecture and CAD for Deep-Submicron FPGAs[M].Wang Lingli,Yang Meng,Zhou Xuegong, trans.Beijing:Publishing House of Electronics Industry,2008:10-11.(in Chinese)
贝兹,马夸特,罗斯.深亚微米FPGA结构与CAD设计[M].王伶俐,杨萌,周学功,译.北京:电子工业出版社,2008:10-11.
[13] Li Shaojun,Wang Zi’ou,Wang Yuanyuan,et al.A novel 6-T SRAM cell design with high reliability and low power[J].Modern Electronics Technique,2011,34(16):123-125,130.(in Chinese)
李少君,王子欧,王媛媛,等.新型高可靠性低功耗6管SRAM单元设计[J].现代电子技术,2011,34(16):123-125,130.
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