[1]李东,敖晟,田劲东,等.基于FPGA的模板滤波IP核的设计与实现[J].深圳大学学报理工版,2018,35(6):622-628.[doi:10.3724/SP.J.1249.2018.06622]
　LI Dong,AO Sheng,TIAN Jindong,et al.Design and implementation of template filtering IP core based on FPGA[J].Journal of Shenzhen University Science and Engineering,2018,35(6):622-628.[doi:10.3724/SP.J.1249.2018.06622]
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基于FPGA的模板滤波IP核的设计与实现()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第35卷
期数:
2018年第6期
页码:
622-628
栏目:
【电子与信息科学】
出版日期:
2018-11-16

文章信息/Info

Title:
Design and implementation of template filtering IP core based on FPGA
文章编号:
201806011
作者:
李东; 敖晟; 田劲东; 田勇
深圳大学光电工程学院，广东深圳51860
Author(s):
LI Dong;  AO Sheng;  TIAN Jindong;  and TIAN Yong
College of Optoelectronic Engineering, Shenzhen University, Shenzhen 51860, Guangdong Province, P.R.China
关键词:
图像处理; 卷积运算; 现场可编程门阵列; 模板滤波; IP核; 卷积结构
Keywords:
image processing;  convolution operation;  field programmable gate array (FPGA);  template filtering;  intellectual property (IP) core;  convolution structure
分类号:
TP 752.1；T 274.2
DOI:
10.3724/SP.J.1249.2018.06622
文献标志码:
A
摘要:
在数字图像处理过程中，二维模板卷积是一种重要的操作．提出一种基于现场可编程门阵列（field programmable gate array, FPGA）的可变模板滤波IP（intellectual property）核的设计方法，通过参数化的循环例化移位寄存器构建可灵活调整窗口大小的缓存结构，采用只读寄存器（read-only memory, ROM）载入模板滤波系数，并利用加法树模块实现快速累加．相比传统组合扩展方法，本设计充分节约了硬件资源，简化了电路设计，提供了便捷的调用接口，只需修改参数便可灵活调整卷积结构，适用于任意窗口大小、任意模板系数、任意图像大小和数据位宽的卷积运算，具有良好的通用性和可维护性．
Abstract:
2D template convolution is an important operation in the field of digital image processing. This paper proposes a new method to design the variable template filtering intellectual property (IP) core based on the field programmable gate array (FPGA). Our method can flexibly adjust the window size with the parameterized loop instantiation shift register construction. The cache structure uses read-only memory (ROM) to load the template filter coefficients and uses the addition tree module to achieve the fast accumulation. Compared with the traditional combination expansion method, the developed method can fully save the hardware resources, simplify the circuit design, provide a convenient call interface, and flexibly adjust the convolution structure. It is also suitable for any window size, arbitrary template coefficients, convolution operation of arbitrary image size and data bit width, and has the good versatility and maintainability.

参考文献/References:

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备注/Memo

备注/Memo:
Received：2017-11-07；Revised：2018-05-23；Accepted：2018-07-24
Foundation：National Natural Science Foundation of China (51775352); Natural Science Foundation of Guangdong Province (2014A030313550)
Corresponding author：Assoiate professor LI Dong.E-mail: lidong@szu.edu.cn
Citation：LI Dong, AO Sheng, TIAN Jindong, et al. Design and implementation of template filtering IP core based on FPGA［J］. Journal of Shenzhen University Science and Engineering, 2018, 35(6): 622-628.（in Chinese）
基金项目：国家自然科学基金资助项目（51775352）；广东省自然科学基金资助项目（2014A030313550）
作者简介：李东（1982—），男，深圳大学副教授、博士．研究方向：机器视觉，嵌入式系统技术．E-mail: lidong@szu.edu.cn
敖晟(1996—)，男，深圳大学硕士研究生．研究方向：机器视觉与图像处理．E-mail：895408584@qq.com
李东、敖晟为共同第一作者．
引文：李东，敖晟，田劲东，等．基于FPGA的模板滤波IP核的设计与实现［J］. 深圳大学学报理工版，2018，35(6)：622-628.
更新日期/Last Update: 2018-11-30