[1]夏银水,王士恒,钱利波.基于M4结构的混合逻辑全加器设计[J].深圳大学学报理工版,2014,31(5):479-486.[doi:10.3724/SP.J.1249.2014.05479]
 Xia Yinshui,Wang Shiheng,and Qian Libo.Full adder design based on hybrid logic of M4 structure[J].Journal of Shenzhen University Science and Engineering,2014,31(5):479-486.[doi:10.3724/SP.J.1249.2014.05479]
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基于M4结构的混合逻辑全加器设计()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第31卷
期数:
2014年第5期
页码:
479-486
栏目:
电子与信息科学
出版日期:
2014-09-20

文章信息/Info

Title:
Full adder design based on hybrid logic of M4 structure
文章编号:
201405006
作者:
夏银水王士恒钱利波
宁波大学信息科学与工程学院,浙江宁波 315211
Author(s):
Xia Yinshui Wang Shiheng and Qian Libo
College of Information Science and Engineering, Ningbo University, Ningbo 315211, Zhejiang Province, P.R.China
关键词:
集成电路技术全加器运算电路混合逻辑低能耗延时功耗延时积
Keywords:
integrated circuit full adder arithmetic circuit hybrid logic low energy consumption delay power delay product
分类号:
TN 4;TN 431.2
DOI:
10.3724/SP.J.1249.2014.05479
文献标志码:
A
摘要:
针对全加器速度和功耗日益突出的矛盾,提出一种基于M4结构的混合逻辑全加器(HLM4-FA)设计方案.通过两个独立的部分分别产生输出信号,减小电路模块间内部信号的输出负载,优化器件的延时.针对不同的模块,采用混合逻辑设计方法,克服单一逻辑设计电路的局限性,降低电路的功耗,从而降低全加器的功耗延时积.与Hybird、Hybird_CMOS和SR_CPL_Buffer全加器相比,延时和功耗延时积减小分别达33%和37%,有效节省了电路能耗.
Abstract:
Against the increasing contradiction between speed and power consumption of full adders, a new full adder design method based on hybrid logic of M4 structure (HLM4-FA) is proposed.By generating output signals with two separate parts,the output load of internal signals between different modules is reduced, and the delay is optimized.The employment of hybrid logic styles for different modules in the design improves the speed, lowers the power consumption,and also reduces the power delay product (PDP).Compared with the Hybird, Hybird_CMOS, and SR_CPL_Buffer full adders,the proposed full adder reduces the delay and PDP by 33% and 37% respectively.

参考文献/References:

[1] Piguet C.Low-power CMOS circuits:technology,logic design and CAD tools[M].Boca Raton(USA):CRC Press Inc,2010.
[2] Ickes N,Gammie G,Sinangil M E,et al.A 28 nm 0.6 V low-power DSP for mobile applications[J].IEEE Journal of Solid-State Circuits,2012,47(1):35-46.
[3] Goyal C,Kumar A.Comparative analysis of energy efficient low power 1 bit full adder at 120 nm technology[J].International Journal of Advances in Engineering & Technology,2012,3(1):501-509.
[4] Purohit S,Margala M.Investigating the impact of logic and circuit implementation on full adder performance[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2012,20(7):1327-1331.
[5] Wairya S, Nagaria R K, Tiwari S. Comparative performance analysis of XOR-XNOR function based high speed CMOS full adder circuits for low voltage VLSI design[J].International Journal of VLSI Design and Communication Systems (VLSICS),2012,3(2):221-242.
[6] Chang C H,Gu J M,Zhang M Y.A review of 0.18-μm full adder performances for tree structured arithmetic circuits[J].IEEE Transactions on Very Large Scale Integration(VLSI) Systems,2005,13(6):686-695.
[7] Zhang M,Gu J M,Chang C H.A novel hybrid pass logic with static CMOS output drive full-adder cell[C]// Proceedings of the International Symposium on Circuits and Systems.Bangkok:IEEE Press,2003,5:317-320.
[8] Aguirre-Hernandez M, Linares-Aranda M. CMOS full-adders for energy-efficient arithmetic applications[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2011,19(4):718-721.
[9] Zimmermann R,Fichtner W.Low-power logic styles:CMOS versus pass-transistor logic[J].IEEE Journal of Solid-State Circuits,1997,32(7):1079-1090.
[10] Meher P,Mahapatra K K.A high speed low noise CMOS dynamic full adder cell[C]// International Conference on Circuits, Controls and Communications (CCUBE).Bengaluru(India):IEEE Press,2013:1-4.
[11] Santanu M,Bishnu P De,Aditya Kr S.Design and implementation of low-power high-performance carry skip adder[J].International Journal of Engineering and Advanced Technology,2012,1(4):212-218.
[12] Divakara P,Ramana R R. A novel 1-bit full adder design using DCVSL XOR/XNOR gate and pass transistor multiplexers[J].International Journal of Innovative Technology and Exploring Engineering(IJITEE),2013,2(4):142-146.
[13] Goel S,Kumar A,Bayoumi M A.Design of robust,energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style[J].IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2006,14(12):1309-1320.
[14] Agarwal S,Pavankumar V K,Yokesh R.Energy-efficient,high performance circuits for arithmetic units[C]// The 21st International Conference on VLSI Design. Hyderabad(India):IEEE Press,2008:371-376.
[15] Chang C H,Gu J,Zhang M.Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits[J].IEEE Transactions on Circuits and Systems,2004,51(10):1985-1997.
[16] Kuang S R, WANG J P, GUO C Y. Modified booth multipliers with a regular partial product array[J].IEEE Transactions on Circuits and Systems II: Express Briefs,2009, 56(5): 404-408.
[17] Abed S, Mohd B J, Al-bayati Z, et al. Low power Wallace multiplier design based on wide counters[J]. International Journal of Circuit Theory and Applications, 2012, 40(11): 1175-1185.
[18] Khatoon S. A novel design for highly compact low power area Efficient 1-bit full adders[J].International Journal of Advances in Engineering & Technology, 2012, 4(2):55-64.

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备注/Memo

备注/Memo:
Received:2013-12-10;Revised:2014-06-15;Accepted:2014-07-09
Foundation:National Natural Science Foundation of China (61131001)
Corresponding author:Professor Xia Yinshui.E-mail:xiayinshui@nbu.edu.cn
Citation:Xia Yinshui,Wang Shiheng,Qian Libo.Full adder design based on hybrid logic of M4 structure[J]. Journal of Shenzhen University Science and Engineering, 2014, 31(5): 479-486.(in Chinese)
基金项目:国家自然科学基金资助项目(61131001)
作者简介:夏银水 (1963— ) ,男(汉族),浙江省余姚市人,宁波大学研究员、博士生导师.E-mail:xiayinshui@nbu.edu.cn
引文:夏银水,王士恒,钱利波.基于M4结构的混合逻辑全加器设计[J]. 深圳大学学报理工版,2014,31(5):479-486.
更新日期/Last Update: 2014-09-11