[1]刘贵宅,于芳,刘忠立,等.扩展型资源共享方案在RTL综合中的实现[J].深圳大学学报理工版,2013,30(No.5(441-550)):456-461.[doi:10.3724/SP.J.1249.2013.05456]
 Liu Guizhai,Yu Fang,et al.Implementation of expanded resource sharing in RTL synthesis[J].Journal of Shenzhen University Science and Engineering,2013,30(No.5(441-550)):456-461.[doi:10.3724/SP.J.1249.2013.05456]
点击复制

扩展型资源共享方案在RTL综合中的实现()
分享到:

《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第30卷
期数:
2013年No.5(441-550)
页码:
456-461
栏目:
电子与信息科学
出版日期:
2013-09-02

文章信息/Info

Title:
Implementation of expanded resource sharing in RTL synthesis
文章编号:
20130503
作者:
刘贵宅12于芳12刘忠立12刁岚松3吴洋12
1)中国科学院微电子研究所,北京 100029
2)中国科学院大学 物理学院,北京100049
3)飘石科技有限公司,北京 100029
Author(s):
Liu Guizhai1 2 Yu Fang1 2 Liu Zhongli1 2 Diao Lansong3 and Wu Yang1 2
1)Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, P.R.China
2)School of Physics, University of Chinese Academy of Sciences, Beijing 100049, P.R.China
3)Uptops Design Technologies Inc, Beijing 100029, P.R.China
关键词:
微电子学现场可编程门阵列资源共享寄存器传输级寄存器传输级综合 算术逻辑单元面积优化逻辑优化
Keywords:
microelectronics resource sharing field programmable gate array register transfer level register transfer level synthesis arithmetic logic unit area optimization logic optimization
分类号:
TN 47;TP 319
DOI:
10.3724/SP.J.1249.2013.05456
文献标志码:
A
摘要:
针对现有寄存器传输级(register transfer level,RTL)综合中资源共享仅针对算术逻辑单元(arithmetic logic unit,ALU)的问题,提出扩展型资源共享的方法.该方法对所有逻辑门进行共享,既可优化ALU,又可优化普通逻辑单元,突破了资源共享基于多路选择器(multiplexer,MUX)的限制,实现算术优化及逻辑优化.实验结果与开源工具ABC比较,LUT数减少了19.2%,表明该方法不仅可减少算术逻辑单元的数目,也可有效减少普通逻辑资源的数目,最终实现面积优化.
Abstract:
A new expanded resource sharing method was proposed to solve the issue that resource sharing is only for arithmetic logic unit (ALU) in RTL synthesis. All kinds of logic cells can be shared to optimize both ALUs and common logic cells. The restrictions of resource sharing based on multiplexer were resolved and the arithmetic and logic optimization were implemented. The results have demonstrated that the number of LUTs was reduced by 19.2% in comparison with open-source ABC. The number of common logic resources was also reduced significantly, which means the purpose of area optimization is achieved.

参考文献/References:

[1] Xia Yuwen.The Design of Verilog HDL Digital[M].2nd edition.Beijing:Electronic Industry Press,2004:201-215.(in Chinese)
夏宇闻.Verilog HDL数字设计[M].2版.北京:电子工业出版社,2004:201-215.
[2] Chen Liang,Li Yan,Li Ming,et al.Implementation and application of navigated place and route for an SRAM-based FPGA[J].Journal of Shenzhen University Science and Engineering,2012,29(3):217-223.(in Chinese)
陈亮,李艳,李明,等.基于SRAM的FPGA导航布局布线方法实现与应用[J].深圳大学学报理工版,2012,29(3):217-223.
[3] Zhang Feng,Li Yan,Han Xiaowei,et al.Design and implementation of an integrated multi-level FPGA design system[J].Journal of Shenzhen University Science and Engineering,2012,29(5):377-385.(in Chinese)
张峰,李艳,韩小炜,等.用于FPGA的多层次集成设计系统的设计与实现[J].深圳大学学报理工版,2012,29(5):377-385.
[4] Cheng Tina.Sieve:An XML-based Structural Verilog Rules Check Tool[D].Cambridge(USA):Massachusetts Institute of Technology,2003:25-29.
[5] Liu Mingye,Zhang Dongxiao,Ye Meilong,et al.The Theory of ASIC High Level Synthesis[M].Beijing:Beijing Institute of Technology Press,1998:179-246.(in Chinese)
刘明业,张东晓,叶梅龙,等.专用集成电路高级综合理论[M].北京:北京理工大学出版社,1998:179-246.
[6] Zhang Qianli,Chen S L C, Li Yan,et al.Mapper design for an SOI-based FPGA[C]// Proceedings of the 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.Shanghai(China):IEEE Press,2010:821-823.
[7] Berkeley Logic Synthesis and Verification Group.ABC:a system for sequential synthesis and verification[DB/OL].Berkeley(USA):University of California.(2005-07-29)[2012-10-15].http://www.eecs.berkeley.edu/~alanmi/abc/
[8] Stephen Williams.Icarus:a Verilog simulation and synthesis tool[CP/OL].(2006-12-26)[ 2012-10-15].http://iverilog.icarus.com/
[9] Jamieson P,Kent K B,Gharibian F,et al.Odin II:an open-source Verilog HDL synthesis tool for CAD research. proceedings[C]// Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.Washington:IEEE Computer Society,2010:149-156.
[10] Synopsis.VHDL Compiler Reference Manual[M].Mountain View(USA):Synopsys,2004.
[11] Aji S,McEliece R.The generalized distributive law[J].IEEE Transactions on Information Theory,2000,46(2):325-343.
[12] Mondal S,Memik S gˇrenci.Resource sharing in pipelined CDFG synthesis[C]// Proceedings of the Asia and South Pacific Design Automation Conference.New York:ACM,2005:795-798.
[13] Yang Saeyang.Logic Synthesis and Optimization Benchmarks User Guide Version 3.0[M].Research Triangle Park:Microelectronics Center of North Carolina(MCNC),1991.
[14] Albrecht C.IWLS 2005 Benchmarks[M].Lake Arrowhead(USA):[s.n.],2005.

相似文献/References:

[1]徐渊,周清海,张智,等.基于FPGA的实时CMOS视频图像预处理系统[J].深圳大学学报理工版,2013,30(No.4(331-440)):416.[doi:10.3724/SP.J.1249.2013.04416]
 Xu Yuan,Zhou Qinghai,Zhang Zhi,et al.FPGA-based real-time CMOS video preprocessing system[J].Journal of Shenzhen University Science and Engineering,2013,30(No.5(441-550)):416.[doi:10.3724/SP.J.1249.2013.04416]
[2]詹从来,龙伟,丁远超,等.基于FPGA的多路数据采集与处理系统设计[J].深圳大学学报理工版,2016,33(2):127.[doi:10.3724/SP.J.1249.2016.02127]
 Zhan Conglai,Long Wei,Ding Yuanchao,et al.Design of multi channel data collection and processing system based on FPGA[J].Journal of Shenzhen University Science and Engineering,2016,33(No.5(441-550)):127.[doi:10.3724/SP.J.1249.2016.02127]
[3]李东,陈烁,田劲东,等.USB2.0工业相机的图像采集鲁棒性研究[J].深圳大学学报理工版,2016,33(5):525.[doi:10.3724/SP.J.1249.2016.05525]
 Li Dong,Chen Shuo,Tian Jindong,et al.The robustness of image capture of USB2.0 industrial camera[J].Journal of Shenzhen University Science and Engineering,2016,33(No.5(441-550)):525.[doi:10.3724/SP.J.1249.2016.05525]
[4]李东,敖晟,田劲东,等.基于FPGA的模板滤波IP核的设计与实现[J].深圳大学学报理工版,2018,35(6):622.[doi:10.3724/SP.J.1249.2018.06622]
 LI Dong,AO Sheng,TIAN Jindong,et al.Design and implementation of template filtering IP core based on FPGA[J].Journal of Shenzhen University Science and Engineering,2018,35(No.5(441-550)):622.[doi:10.3724/SP.J.1249.2018.06622]
[5]陈亮,李艳,李明,等.基于SRAM的FPGA导航布局布线方法实现与应用[J].深圳大学学报理工版,2012,29(No.3(189-282)):217.[doi:10.3724/SP.J.1249.2012.03217]
 CHEN Liang,LI Yan,LI Ming,et al.Implementation and application of navigated place and route for an SRAM-based FPGA[J].Journal of Shenzhen University Science and Engineering,2012,29(No.5(441-550)):217.[doi:10.3724/SP.J.1249.2012.03217]
[6]张峰,李艳,韩小炜,等.用于FPGA的多层次集成设计系统的设计与实现[J].深圳大学学报理工版,2012,29(No.5(377-470)):377.[doi:10.3724/SP.J.1249.2012.05377]
 ZHANG Feng,LI Yan,HAN Xiao-wei,et al.Design and implementation of an integrated multi-level FPGA design system[J].Journal of Shenzhen University Science and Engineering,2012,29(No.5(441-550)):377.[doi:10.3724/SP.J.1249.2012.05377]
[7]郭旭峰,王作建,李明,等.具有MUX模式的新型LUT结构及其优化算法[J].深圳大学学报理工版,2013,30(No.3(221-330)):248.[doi:10.3724/SP.J.1249.2013.03248]
 Guo Xufeng,Wang Zuojian,Li Ming,et al.A new LUT construct with MUX mode and the corresponding optimization algorithm[J].Journal of Shenzhen University Science and Engineering,2013,30(No.5(441-550)):248.[doi:10.3724/SP.J.1249.2013.03248]

备注/Memo

备注/Memo:
Received:2012-11-08;Revised:2013-04-15;Accepted:2013-08-01
Corresponding author:Professor Yu Fang. E-mail: yufang@red.semi.ac.cn
Citation:Liu Guizhai,Yu Fang,Liu Zhongli,et al.Implementation of expanded resource sharing in RTL synthesis[J]. Journal of Shenzhen University Science and Engineering, 2013, 30(5): 456-461.(in Chinese)
作者简介:刘贵宅(1984-),男(汉族) ,河北省晋州市人,中国科学院大学博士研究生.E-mail:laker456@163.com
引文:刘贵宅,于芳,刘忠立,等.扩展型资源共享方案在RTL综合中的实现[J]. 深圳大学学报理工版,2013,30(5):456-461.
更新日期/Last Update: 2013-09-02