[1]戴鹏,王明江,王新安.基于视频编解码的可重构处理器存储系统设计[J].深圳大学学报理工版,2013,30(No.2(111-220)):150-156.[doi:10.3724/SP.J.1249.2013.02150]
 Dai Peng,Wang Mingjiang,and Wang Xinan.Design of reconfigurable processor memory system for video codec[J].Journal of Shenzhen University Science and Engineering,2013,30(No.2(111-220)):150-156.[doi:10.3724/SP.J.1249.2013.02150]
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基于视频编解码的可重构处理器存储系统设计()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第30卷
期数:
2013年No.2(111-220)
页码:
150-156
栏目:
电子与信息科学
出版日期:
2013-03-18

文章信息/Info

Title:
Design of reconfigurable processor memory system for video codec
作者:
戴鹏1王明江1王新安2
1)哈尔滨工业大学深圳研究生院,深圳 518055
2)北京大学深圳研究生院,深圳 518055
Author(s):
Dai Peng1 Wang Mingjiang1 and Wang Xin’an2
1)Shenzhen Graduate School, Harbin Institute of Technology, Shenzhen 518055, P.R.China
2)Peking University Shenzhen Graduate School, Shenzhen 518055, P.R.China
关键词:
集成电路技术可重构处理器数字信号处理离散余弦变换存储器多媒体处理视频编解码
Keywords:
integrated circuit technology reconfigurable processor digital signal processing discrete cosine transform memory multimedia processing video codec
分类号:
TN 47;TN 492
DOI:
10.3724/SP.J.1249.2013.02150
文献标志码:
A
摘要:
针对可重构视频编解码处理器ReMAP-2在高清视频编解码应用中对大规模数据吞吐率的需求,提出一种由全双工的帧缓存器及DMA组成的高速存储系统.其中帧缓存器由2个4 kbyte存储器构成,每个存储器分为16个存储块,采用二维地址编码,通过数据排列开关对像素数据的重排序,可满足视频编解码算法对子块像素数据快速读取的需求.仿真实验表明,该存储系统可满足可重构处理器ReMAP-2面向高清视频编解码的高性能处理应用需求.
Abstract:
A high-speed memory system is proposed for reconfigurable codec processor to access high data throughput rates in video codec applications.The full duplex frame buffer and DMA are included in this new memory system.The frame buffer contains two memories with the size of 4 kbyte and is divided into 16 banks.Two-dimensional address coding is introduced as well as data arrangement switch for fast sequential data access by codec algorithm.The simulation result shows that the memory system can meet high performance requirement for reconfigurable processor ReMAP-2 in high-definition video codec application.

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备注/Memo

备注/Memo:
Received:2012-02-19;Revised:2013-01-09;Accepted:2013-02-25
Foundation:National Science Foundation for Post-doctoral Scientists of China (20110491091); Shenzhen Technology Research Foundation for Basic Project (JC201105160591A)
Corresponding author:Professor Wang Mingjiang.E-mail:mjwang@hit.edu.cn
Citation:Dai Peng,Wang Mingjiang,Wang Xin’an.Design of reconfigurable processor memory system for video codec[J]. Journal of Shenzhen University Science and Engineering, 2013, 30(2): 150-156.(in Chinese)

基金项目:国家博士后基金资助项目(20110491091); 深圳市科技基础研究基金资助项目(JC201105160591A)
作者简介:戴鹏(1983-),男(苗族),湖南省双峰县人,哈尔滨工业大学博士后研究人员.E-mail:daiowen@126.com
引文:戴鹏,王明江,王新安.基于视频编解码的可重构处理器存储系统设计[J]. 深圳大学学报理工版,2013,30(2):150-156.
更新日期/Last Update: 2013-03-19