[1]张峰,李艳,韩小炜,等.用于FPGA的多层次集成设计系统的设计与实现[J].深圳大学学报理工版,2012,29(No.5(377-470)):377-385.[doi:10.3724/SP.J.1249.2012.05377]
 ZHANG Feng,LI Yan,HAN Xiao-wei,et al.Design and implementation of an integrated multi-level FPGA design system[J].Journal of Shenzhen University Science and Engineering,2012,29(No.5(377-470)):377-385.[doi:10.3724/SP.J.1249.2012.05377]
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用于FPGA的多层次集成设计系统的设计与实现()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第29卷
期数:
2012年No.5(377-470)
页码:
377-385
栏目:
电子与信息科学
出版日期:
2012-09-21

文章信息/Info

Title:
Design and implementation of an integrated multi-level FPGA design system
作者:
 张峰 李艳 韩小炜 李明 张倩莉 陈亮 吴利华 张国全 刘贵宅 郭旭峰 杨波 赵岩 王剑 李建忠 于芳 刘忠立
中国科学院微电子研究所, 北京 100029
Author(s):
ZHANG Feng LI Yan HAN Xiao-wei LI Ming ZHANG Qian-li CHEN Liang WU Li-hua ZHANG Guo-quan LIU Gui-zhai GUO Xu-feng YANG Bo ZHAO Yan WANG Jian LI Jian-zhong YU Fang and LIU Zhong-li
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, P.R.China
关键词:
微电子学现场可编程门阵列电子设计自动化集成设计系统用户图形界面架构设计版图设计系统级设计芯片仿真芯片板级测试
Keywords:
microelectronics field programmable gate array electronic design automation integrated design system graphical user interface architecture design layout design system level design chip simulation system level test
分类号:
TN 47;TP 319
DOI:
10.3724/SP.J.1249.2012.05377
文献标志码:
A
摘要:
针对当前现场可编程门阵列(fieldprogrammablegatearray,FPGA)领域,电子设计自动化(electronic design automation, EDA)工具集成度不够高、不具备用户自主设计FPGA芯片的功能等问题,设计并实现一套完整的FPGA多层次集成设计系统(versatile design system, VDS).该系统包括高度集成的设计开发环境和FPGA芯片级到系统级的设计与验证工具,为设计、应用和验证自主研发的FPGA芯片提供了一个有效平台.VDS的显著特点在于提供了全自动芯片生成功能,使用户能根据自身需要灵活控制芯片的规模和功能,快速开发一系列的适应不同应用的FPGA.借助VDS成功设计出两款FPGA芯片,通过对FPGA进行电路设计以及对芯片和应用进行仿真与验证,证明了VDS的有效可行.
Abstract:
In modern FPGA-EDA design system, custom design of the FPGA chip is impossible due to inadequate tools. A complete FPGA multi-level integrated design system, versatile design system (VDS), was developed. The VDS contains a highly integrated development environment, which includes design and verification tools for FPGA designs from the chip-level to the system-level. A VDS provides an efficient platform for FPGA design, verification and application development. A remarkable characteristic of VDS is that it supports fully automatic generation for the FPGA chip and allows users to flexibly control the chip’s size and function according to their requirements. Finally, two FPGA chips were successfully designed by the VDS, and the experiment results of the design, simulation and verification have demostrated the efficiency of VDS.

参考文献/References:

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备注/Memo

备注/Memo:
Received:2012-05-09;Revised:2012-08-28
Corresponding author:Professor YU Fang. E-mail: yufang@ime.ac.cn
Citation:ZHANG Feng,LI Yan,HAN Xiao-wei,et al.Design and implementation of an integrated multi-level FPGA design system[J]. Journal of Shenzhen University Science and Engineering, 2012, 29(5): 377-385.(in Chinese)
作者简介:张峰(1987-),男(汉族),安徽省宿州市人,中国科学院微电子研究所博士研究生.E-mail:zhangfeng08@yeah.net
引文:张峰,李艳,韩小炜,等.用于FPGA的多层次集成设计系统的设计与实现[J]. 深圳大学学报理工版,2012,29(5):377-385.
更新日期/Last Update: 2012-09-26