[1]黄俊,朱明程. 局部动态重构在SOPC中的应用[J].深圳大学学报理工版,2006,23(4):351-355.
　HUANG Jun and ZHUMing-cheng.The application of partial reconfiguration in SOPC[J].Journal of Shenzhen University Science and Engineering,2006,23(4):351-355.
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第23卷
期数:
2006年4期
页码:
351-355
栏目:
土木建筑工程
出版日期:
2006-10-30

文章信息/Info

Title:
The application of partial reconfiguration in SOPC
文章编号:
1000-2618（2006）04-0351-05
作者:
黄俊; 朱明程
深圳大学信息工程学院，深圳518060
Author(s):
HUANG Jun and ZHUMing-cheng
College of Information Engineering Shenzhen University Shenzhen 518060P. R. China
关键词:
动态重构; 现场可编程逻辑阵列; OPB总线; 局部重构
Keywords:
dynamic reconfiguration;  field programmable gate array; on-chip peripheral bus; partial reconfiguration
分类号:
TP 30
文献标志码:
A
摘要:
提出一种在Xilinx平台上基于模块的局部重构设计方法，并将其应用在片上可编程系统SOPC中.在现有Xilinx软硬件平台上，以XC2VP40内嵌的PowerPC处理器内核为基础，通过XC2VP40内部配置访问通道（ICAP），对挂在OPB总路线上的DCT IP模块和IDCT IP模块进行动态重构.该方法实现了局部重构技术在SOPC中的应用，及FPGA硬件资源的高速时分复用，降低了系统功耗，提高了系统硬件资源的利用率.
Abstract:
An algorithm of module-based partial reconfiguration on Xilinx and its application in system on programmable chip (SOPC) was introduced. On the hardware and software platform of Xilinx, Power PC embedded in the XC2VP40 dynamically reconfigures DCT IP modular and IDCT IP modular by internal configuration access port (ICAP). DCT IP modular and IDCT IP modular could be connected with on-chip peripheral bus (OPB). So it realizes high-speed time division multiplex on FPGA hard resources, and reduces power dissipation. At the same time, it improves the usage of FPGA hardware resources.

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更新日期/Last Update: 2015-06-26