[1]黄影,张春元,刘东.基于FPGA双机容错系统的设计与实现[J].深圳大学学报理工版,2006,23(2):112-116.
 HUANG Ying,ZHANG Chun-yuan,and LIU Dong.Design and implementation of the dual fault-tolerant system based on the FPGA[J].Journal of Shenzhen University Science and Engineering,2006,23(2):112-116.
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基于FPGA双机容错系统的设计与实现()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第23卷
期数:
2006年2期
页码:
112-116
栏目:
土木建筑工程
出版日期:
2006-04-30

文章信息/Info

Title:
Design and implementation of the dual fault-tolerant system based on the FPGA
文章编号:
1000-2618(2006)02-0112-05
作者:
黄影张春元刘东
国防科技大学计算机学院,长沙 410073
Author(s):
HUANG Ying ZHANG Chun-yuan and LIU Dong
Department of Computer, National University of Defense Technology, Changsha Hunan 410073, P. R. China
关键词:
双机容错温备现场可编程逻辑门电路
Keywords:
dual fault-tolerant warm-backup field program gate array
分类号:
TP 302.8
文献标志码:
A
摘要:
根据双机容错技术常用方案及特点 , 结合现场可编程逻门电路 (FPGA) 程的特性及相关技术 , 提出并实现了基于 FPGA 双机容错系统的设计方案 . 仲裁器机制根据双机工作的监测信号负责完成主备机切换功能 . 系统在实现过程中 , 利用 FPGA 内部时钟信号 clk“ 同步化 异步信号 , 不但充分发挥了 FPGA 的内部资源 , 且避免了因信号毛刺可能产生的电路错误 . 仿真结果表明 , 该双机容错机制的设计方案能完成系统所需功能 , 可靠性较好 .
Abstract:
Dual fault - tolerant technique , a key technique to improve reliability of computer system , is widely applied in the design and development of embedded system. Based on various methods in common use and combined with correlative techniques of programmable devices , a scheme of the dual fault - tolerant system based on FPGA is presented. The arbitrator mechanism is important for the real implementation because it supervises the switches between the host and the backup machine. In the process of implementation , not only FPGA s inner resources were fully made use of , but also the circuit mistake s caused by signals burrs w ere avoided using FPGA s inner clock signal to make the asynchronous signals synchronized. The simulational result shows good performance.
更新日期/Last Update: 2015-06-26