[1]王新安,叶兆华,戴鹏,等.可重构阵列DSP结构ReMAP[J].深圳大学学报理工版,2010,27(1):16-20.
 WANG Xin-an,YE Zhao-hua,DAI Peng,et al.ReMAP:a reconfigurable array DSP architecture[J].Journal of Shenzhen University Science and Engineering,2010,27(1):16-20.
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可重构阵列DSP结构ReMAP()
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《深圳大学学报理工版》[ISSN:1000-2618/CN:44-1401/N]

卷:
第27卷
期数:
2010年1期
页码:
16-20
栏目:
光电与信息工程
出版日期:
2010-01-31

文章信息/Info

Title:
ReMAP:a reconfigurable array DSP architecture
文章编号:
1000-2618(2010)01-0016-05
作者:
王新安叶兆华戴鹏周丹
北京大学深圳研究生院 集成微系统科学工程与应用国家重点实验室,深圳518055
Author(s):
WANG Xin-anYE Zhao-huaDAI Pengand ZHOU Dan
The State Key Laboratory of Integrated Microsystems,Peking University Shenzhen Graduate School,Shenzhen 518055,P.R.China
关键词:
计算机工程可重构阵列处理器计算密集型处理器数字信号处理多媒体处理
Keywords:
computer projectReMAPcomputer-intensive processordigital signal processingmultimedia processing
分类号:
TN 47;TP 302
文献标志码:
A
摘要:
为满足多媒体处理等领域要求芯片高性能,且开发周期短的需求,提出一种可重构阵列DSP的结构——ReMAP.该阵列结构由多个运算单元、存储器和交换开关等级联组成,易于扩展和配置.通过把算法分割映射到多个运算单元之中,提高芯片对计算密集型任务的执行效率.在SMIC 0.18 μm工艺下完成了ReMAP芯片的原型验证,包含16个ALU单元.测试结果表明,该结构能以较高效率完成如SAD和DCT等视频处理相关算法.
Abstract:
Current IC design,especially that for multimedia processing,requires high performance and short development time.To satisfy these design requirements for an optimal time-to-market,a reconfigurable Array DSP architecture (ReMAP) with processing elements,memory,switch,and other components was proposed.Pipeline reconfiguration was introduced for performance improvement of applications.The antitype chip with 2×2 PEs was fabricated in SMIC 0.18 μm CMOS,which contains 16 reALUs.Some common algorithms such as DCT and SAD were implemented in ReMAP.The result shows that the architecture can support high performance implementation of media processing.

参考文献/References:


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备注/Memo

备注/Memo:
收稿日期:2009-05-12;修回日期:2009-09-24
基金项目:国家高技术研究发展计划资助项目(2009AA01Z127);深圳市科技计划项目(SZKJ-2007017)
作者简介:王新安(1963-),男(汉族),河南省上蔡县人,北京大学深圳研究生院教授、博士生导师.E-mail:wangxa@szpku.edu.cn
更新日期/Last Update: 2010-02-06